The present invention relates to a conditioning circuit for selectively buffering an input signal to a signal processing circuit for subsequent processing thereof, and in particular though not limited to a conditioning circuit for selectively buffering an input signal to an analog-to-digital converter. The invention also relates to a signal processing circuit comprising the conditioning circuit, and to an analog-to-digital converter circuit comprising the conditioning circuit.
In this specification the terms differential and pseudo-differential are used in connection with input signals. Differential signals are of the type which require two terminals per signal, since the signal is represented as the difference between the voltages on two terminals. The two terminals are respectively referred to as the positive and negative terminals. An example of a differential signal, is one which is sourced from a circuit of bridge configuration where the differential signal swings around a mid-point or reference voltage of Vbridge/2, where Vbridge is the voltage applied to the bridge, The voltages of a differential signal generally do not approach the respective supply rail voltages of a circuit, and have a source impedance arising from resistors which form the bridge circuit. Pseudo-differential signals are signals which share a common terminal, which may be negative or positive but generally is negative. Thus, pseudo-differential signals require N+1 terminals per N signals. Commonly, pseudo-differential signals are also referred to as single-ended signals. Additionally, in this specification a reference to a positive signal is intended to mean a reference to the signal applied to the positive terminal, and a reference to a negative signal is intended to mean a reference to the signal applied to the negative terminal. For differential signals the term positive or negative is a convention, rather than being indicative of polarity. If the positive signal is greater than the negative signal, then the differential signal has a positive polarity, Conversely, if the positive signal is less than the negative signal, the differential signal has a negative polarity. For pseudo-differential signals, the negative signal is normally at or close to ground, and the positive signal is above the negative signal, thus giving a pseudo-differential signal of positive polarity.
Signal processing circuits, for example, analog-to-digital converter (ADC) circuits, and in particular, sigma-delta ADC circuits, in general, present a low impedance to an input signal to be processed when applied to input terminals of the ADC circuit. This causes current to flow to or from the input terminals of the ADC circuit, thus leading to a change in voltage of the input signal. This is a particularly serious problem where the input signal is derived from a high impedance source, which is high relative to the impedance presented by the ADC circuit. Any significant change in the voltage of an input signal when it is applied to an ADC circuit or other signal processing circuit is undesirable,
Buffers are commonly used to overcome this problem. A buffer presents a high impedance to an input signal, and buffers are selected so that the input impedance of the buffer is high relative to that of the source impedance of the input signal, thus, leading to minimal change in the voltage of the input signal when applied to the buffer. However, buffers suffer from a number of disadvantages. They tend to add noise and other distortions to the input signal, and the output voltage from a buffer may be offset from the input voltage. Most importantly, buffers in general, can only operate over a limited input voltage range, They are unsuitable for buffering input signals the voltage of which is relatively close to either the positive or negative supply voltage to the buffer. Where the voltage of an input signal is relatively close to the positive or negative supply voltage to the buffer the problems of noise and distortion as well as voltage offset become unacceptable. Indeed, in general, the problem of noise, distortion and voltage offset occurs over a voltage range which is close to one of the positive or negative supply voltages of the buffer, rather than the other. In other words, buffers, in general, can operate with input signal voltages closer to one of the supply voltages of the buffer than the other supply voltage. This, in general, results from the type of transistors with which the input stage of the buffer is implemented. If the input stage of the buffer is implemented in PMOS transistors, the voltage range, over which the buffer can operate, in general, extends doser to the negative supply voltage of the buffer than to the positive supply voltage, and vice versa when the input stage is implemented in NMOS transistors. In other words, when the input stage is implemented in NMOS transistors, the voltage range, over which the buffer can operate, in general, extends closer to the positive supply voltage of the buffer than to the negative supply voltage.
Where a differential input signal is buffered to an ADC circuit, the problems which have just been discussed relating to buffers may not arise, since the positive and negative component signals of the differential signal vary on either side of a reference voltage, which can be selected to lie in the middle of the operating voltage range of the buffer, and the buffer can be selected so that the positive and negative voltage extremes of the positive and negative component signals of the differential signal remain within the operating voltage range of the buffer. However, where an ADC circuit, or indeed any other signal processing circuit must be capable of handling both differential signals, and pseudo-differential signals, and the common voltage of the pseudo-differential signals is relatively close to one or other of the positive or negative supply voltage of the buffer, buffering of the respective input signals is unsatisfactory. This is due to the fact that the buffered output of the common input signal will be unsuitable for further processing as a result of noise, distortion and/or voltage offset introduced by the buffer.
There is therefore a need for a conditioning circuit for selectively buffering an input signal to an ADC circuit, and indeed, to other signal processing circuits for processing the input signals, which overcomes these problems.
The present invention is directed towards providing such a conditioning circuit, as well as a signal processing circuit and an ADC circuit both of which comprise the conditioning circuit.
According to the invention there is provided a conditioning circuit for selectively buffering an input signal to a signal processing circuit, the conditioning circuit comprising:
a buffer circuit for receiving and buffering the input signal,
a bypass circuit for receiving the input signal, and for bypassing the buffer circuit, and
a control circuit for selecting one of the buffer circuit and the bypass circuit for passing the input signal to the signal processing circuit, so that the input signal is applied to the signal processing circuit through the bypass circuit when the voltage of the input signal falls outside the operating voltage range of the buffer circuit.
In one embodiment of the invention a plurality of input signals are selectively applied to the conditioning circuit, and the control circuit is responsive to which of the input signals is selected for selecting the one of the buffer circuit and the bypass circuit. Preferably, the signals are applied to the conditioning circuit in response to a select signal, and the control circuit is responsive to the select signal for selecting the one of the buffer circuit and the bypass circuit.
In another embodiment of the invention the control circuit is responsive to the input signal for selecting the one of the buffer circuit and the bypass circuit
In another embodiment of the invention the control circuit is responsive to the voltage of the input signal for selecting the one of the buffer circuit and the bypass circuit.
In one embodiment of the invention the control circuit comprises a primary comparing circuit for comparing the voltage of the input signal with a reference voltage for determining if the voltage of the input signal is within the operating voltage range of the buffer circuit, and the control circuit is responsive to the primary comparing circuit for selecting the one of the buffer circuit and the bypass circuit. Preferably, the primary comparing circuit comprises a first primary comparator for comparing the voltage of the input signal with a first reference voltage for determining if the voltage of the input signal exceeds an upper operating voltage limit of the operating voltage range of the buffer circuit, and a second primary comparator for comparing the voltage of the input signal with a second reference voltage for determining if the voltage of the input signal is below a lower operating voltage limit of the operating voltage range of the buffer circuit, the first reference voltage being higher than the second reference voltage.
In another embodiment of the invention the buffer circuit comprises a first buffer circuit and a second buffer circuit connected in parallel, the first and second buffer circuits having respective overlapping operating voltage ranges, the operating voltage range of the first buffer circuit having an upper operating voltage limit higher than the upper operating voltage limit of the second buffer circuit, and the operating voltage range of the second buffer circuit having a lower operating voltage limit lower than the lower operating voltage limit of the first buffer circuit, the respective first and second buffer circuits being alternately selectable so that if the voltage of the input signal exceeds the upper operating voltage limit of the second buffer circuit, the input signal is passed through the first buffer circuit, and if the voltage of the input signal falls below the lower operating voltage limit of the first buffer circuit, the input signal is passed through the second buffer circuit.
Preferably, the control circuit comprises a secondary comparator for comparing the voltage of the input signal with an intermediate reference voltage, the control circuit being responsive to the secondary comparator for selecting one of the first and second buffer circuits for passing the input signal to the signal processing circuit. Advantageously, the intermediate reference voltage is selected to lie between the lower operating voltage limit of the first buffer circuit and the upper operating voltage limit of the second buffer circuit.
In another embodiment of the invention a primary switching circuit is provided for selectively switching the input signal through the one of the buffer circuit and the bypass circuit, the primary switching circuit being responsive to the control circuit for selecting the one of the buffer circuit and the bypass circuit through which the input signal is to be passed to the signal processing circuit, Preferably, the primary switching circuit comprises a first primary switch located in the buffer circuit for isolating the buffer circuit from the signal processing circuit, and a second primary switch located in the bypass circuit for isolating the bypass circuit from the signal processing circuit, the respective first and second primary switches being responsive to the control circuit such that when one of the first and second primary switches is in a closed circuit state for selecting the corresponding one of the buffer circuit and the bypass circuit, the other of the first and second primary switches is in an open circuit state.
In one embodiment of the invention a secondary switching circuit is provided for selectively passing the input signal through one of the first and second buffer circuits.
In one embodiment of the invention the first and second buffer circuits each comprise an operational amplifier.
In another embodiment of the invention the first and second buffer circuits each have a gain of one.
In another embodiment of the invention each first and second primary switch comprises a primary transmission gate switch, and preferably, each primary transmission gate switch comprises a complementary pair of N-type and P-type primary switches.
In one embodiment of the invention the control circuit is responsive to an externally generated control signal for selecting the one of the buffer circuit and the bypass circuit.
In a further embodiment of the invention the conditioning circuit is implemented as an integrated circuit, and may be implemented as a complementary metal oxide semiconductor circuit.
In a further embodiment of the invention the conditioning circuit is adapted for selectively buffering an input signal to an analog to digital converter.
The invention also provides a circuit comprising:
a signal processing circuit for processing a plurality of input signals,
a main switch circuit for selectively switching at least one of the plurality of input signals to the signal processing circuit, and
at least one conditioning circuit for selectively buffering the input signals received from the main switch circuit to the signal processing circuit, each conditioning circuit comprising:
a buffer circuit for buffering the input signals,
a bypass circuit for bypassing the buffer circuit, and
a control circuit for selecting one of the buffer circuit and the bypass circuit for passing the selected input signals to the signal processing circuit, so that the input signals the voltage of which fall outside the operating range of the buffer circuit, are passed to the signal processing circuit through the bypass circuit.
In one embodiment of the invention the signal processing circuit comprises two input terminals for receiving positive signals of the selected input signals and negative signals of the selected input signals from the main switch circuit, and the conditioning circuit is located for passing the positive or negative signals of the selected input signals from the main switch circuit to one of the input terminals of the signal processing circuit.
In another embodiment of the invention one of the input terminals of the signal processing circuit is a positive input terminal, and the other input terminal of the signal processing circuit is a negative input terminal, and two conditioning circuits are provided, one conditioning circuit being located for passing either the positive or negative signals of the selected input signals from the main switch circuit to the positive input terminal of the signal processing circuit, and the other conditioning circuit being located for passing the others of the positive and negative signals of the selected input signals from the main switch circuit to the negative input terminal of the signal processing circuit.
In a further embodiment of the invention the main switch circuit is operable for alternately applying the positive and negative signals of the selected input signals to each of the positive and negative input terminals of the signal processing circuit.
In one embodiment of the invention the main switch circuit is responsive to a select signal for selecting the input signals, and the control circuit of each conditioning circuit is responsive to the select signal for selecting the one of the buffer circuit and the bypass circuit.
In another embodiment of the invention the control circuit of each conditioning circuit is responsive to the voltage of the selected input signal received by the conditioning circuit for selecting the one of the buffer circuit and the bypass circuit
In one embodiment of the invention the control circuit of each conditioning circuit comprises a primary comparing circuit for comparing the voltage of the input signal received by the conditioning circuit with a reference voltage for determining if the voltage of the input signal is within the operating voltage range of the buffer circuit, and the control circuit is responsive to the primary comparing circuit for selecting the one of the buffer circuit and the bypass circuit. Preferably, the primary comparing circuit of each conditioning circuit comprises a first primary comparator for comparing the voltage of the input signal received by the conditioning circuit with a first reference voltage for determining if the voltage of the input signal exceeds an upper operating voltage limit of the operating voltage range of the buffer circuit, and a second primary comparator for comparing the voltage of the input signal with a second reference voltage for determining if the voltage of the input signal is below a lower operating voltage limit of the operating voltage range of the buffer circuit, the first reference voltage being higher than the second reference voltage.
Ideally, the buffer circuit of each conditioning circuit comprises a first buffer circuit and a second buffer circuit connected in parallel, the first and second buffer circuits having respective overlapping operating voltage ranges, the operating voltage range of the first buffer circuit having an upper operating voltage limit higher than the upper operating voltage limit of the second buffer circuit, and the operating voltage range of the second buffer circuit having a lower operating voltage limit lower than the lower operating voltage limit of the first buffer circuit, the respective first and second buffer circuits being alternately selectable so that if the voltage of the input signal exceeds the upper operating voltage limit of the second buffer circuit, the input signal is passed through the first buffer circuit, and if the voltage of the input signal falls below the lower operating voltage limit of the first buffer circuit, the input signal is passed through the second buffer circuit.
In one embodiment of the invention the control circuit of each conditioning circuit comprises a secondary comparator for comparing the voltage of the input signal received by the conditioning circuit with an intermediate reference voltage, the control circuit being responsive to the secondary comparator for selecting one of the first and second buffer circuits for passing the input signal to the signal processing circuit.
In another embodiment of the invention each conditioning circuit comprises a primary switching circuit for selectively switching each input signal received by the conditioning circuit through the one of the buffer circuit and the bypass circuit, the primary switching circuit being responsive to the control circuit for selecting the one of the buffer circuit and the bypass circuit through which the input signal is to be passed to the signal processing circuit.
In a further embodiment of the invention each conditioning circuit comprises a secondary switching circuit for selectively passing the input signal received by the conditioning circuit through one of the first and second buffer circuits.
In one embodiment of the invention the signal processing circuit is an analog to digital converter.
In another embodiment of the invention the signal processing circuit is adapted for processing differential input signals and pseudo-differential input signals.
In another embodiment of the invention the analog to digital converter is a chopped analog to digital converter, and the main switch circuit is responsive to a chop signal outputted by the analog to digital converter for switching respective positive and negative signals of the selected ones of the input signals alternately to the positive and negative input terminals of the analog to digital converter, the control circuit being responsive to the chop signal for selecting the one of the buffer circuit and the conditioning circuit.
In a further embodiment of the invention the circuit is implemented as an integrated circuit.
Further the invention provides an analog to digital converter circuit comprising:
an analog to digital converter for converting a plurality of analog input signals to digital signals,
a main switch circuit for selectively switching at least one of the plurality of analog input signals to the analog to digital converter, and
at least one conditioning circuit for receiving and selectively buffering the input signals received from the main switch circuit to the analog to digital converter, each conditioning circuit comprising:
a buffer circuit for buffering the input signals,
a bypass circuit for bypassing the buffer circuit, and
a control circuit for selecting one of the buffer circuit and the bypass circuit for passing the selected input signals to the analog to digital converter, so that the input signals, the voltage of which fall outside the operating range of the buffer circuit, are passed to the analog to digital converter through the bypass circuit.
In one embodiment of the invention in a sampling phase of a conversion cycle of the analog to digital converter an input capacitor is charged in response to a coarse phase signal and a fine phase signal, and the control circuit is responsive to the coarse phase signal so that the buffer circuit of each conditioning circuit is always selected during the coarse charging phase of the input capacitor of the analog to digital converter.
In another embodiment of the invention a primary switching circuit is provided for selectively switching the input signals through the one of the buffer circuit and the bypass circuit of each conditioning circuit, the primary switching circuit being responsive to the control circuit for selecting the one of the buffer circuit and the bypass circuit through which the input signal is to be passed to the analog to digital converter.
In a further embodiment of the invention the primary switching circuit is implemented by switches of the analog to digital converter.
The invention also provides a method for buffering an input signal to a signal processing circuit, the method comprising the steps of:
providing a buffer circuit for buffering the input signal to the conditioning circuit,
providing a bypass circuit for bypassing the buffer circuit, and
selecting one of the buffer circuit and the bypass circuit for passing the input signal to the signal processing circuit so that the input signal is applied to the signal processing circuit through the bypass circuit when the voltage of the input signal falls outside the operating voltage range of the buffer circuit.
The advantages of the invention are many. A particularly important advantage of the invention is that the conditioning circuit according to the invention provides a relatively simple non-complex circuit for selectively buffering signals to a signal processing circuit, such that only those input signals the voltage of which is within the operating range of the buffer circuit are buffered. Input signals which fall outside the operating range of the buffer circuit are not buffered, and are passed directly to the signal processing circuit. By virtue of the fact that the control circuit is responsive to the input signals, the appropriate one of the buffer circuit and the bypass circuit is selected automatically without the need for any human intervention.